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preliminary 8-mbit (512k x 16) static ram cy7c1051dv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00063 rev. *c revised march 9, 2007 features ? high speed ?t aa = 10 ns ? low active power ?i cc = 110 ma @ 10 ns ? low cmos standby power ?i sb2 = 20 ma ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in lead-free 48-ball fbga and 44-pin tsop ii packages functional description [1] the cy7c1051dv33 is a high-performance cmos static ram organized as 512k words by 16 bits. write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 ?io 7 ), is written into the location specified on the address pins (a 0 ?a 18 ). if byte high enable (bhe ) is low, then data from io pins (io 8 ?io 15 ) is written into the location specified on the address pins (a 0 ?a 18 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on io 0 ?io 7 . if byte high enable (bhe ) is low, then data from memory will appear on io 8 to io 15 . see the ?truth table? on page 8 for a complete description of read and write modes. the input/output pins (io 0 ?io 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or a write operation (ce low, and we low) is in progress. the cy7c1051dv33 is available in a 44-pin tsop ii package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (fbga) package. note 1. for guidelines on sram system design, pleas e refer to the ?system desi gn guidelines? cypress applic ation note, available on t he internet at www.cypress.com . 14 15 logic block diagram a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 512k 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 18 a 9 a 10 io 0 ?io 7 oe io 8 ?io 15 ce we ble bhe [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 2 of 11 \ selection guide ?10 unit maximum access time 10 ns maximum operating current 110 ma maximum cmos standby current 20 ma pin configurations [2] 48-ball mini fbga we v cc a 11 a 10 nc a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe v ss a 7 io 0 bhe nc a 17 a 2 a 1 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 (top view) tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 io 15 a 2 ce io 2 io 0 io 1 bhe a 3 a 4 18 17 20 19 io 3 27 28 25 26 22 21 23 24 v ss io 6 io 4 io 5 io 7 a 16 a 15 ble v cc io 14 io 13 io 12 io 11 io 10 io 9 io 8 a 14 a 13 a 12 a 11 a 9 a 10 a 18 (top view) note 2. nc pins are not connected on the die [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 3 of 11 maximum ratings (exceeding the maximum ratings may impair the useful life of the device. these are for user guidelines, they are not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.3v to v cc + 0.3v dc input voltage [3] .................................?0.3v to v cc + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c3.3v 0.3v dc electrical characteristics over the operating range parameter description test conditions ?10 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il [3] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max, f = f max = 1/t rc 100 mhz 110 ma 83 mhz 100 66 mhz 90 40 mhz 80 i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 20 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 12 pf c out io capacitance 12 pf notes 3. v il (min) = ?2.0v and v ih (max) = v cc + 2.0v for pulse durations of less than 20 ns. 4. tested initially and after any design or proc ess changes that may affect these parameters thermal resistance [4] parameter description test conditions fbga package tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 28.31 51.43 c/w jc thermal resistance (junction to case) 11.4 15.8 c/w [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 4 of 11 ac test loads and waveforms [5] ac switching characteristics [6] over the operating range parameter description ?10 unit min max read cycle t power [7] v cc (typical) to the first access 100 s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce low to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z 0 ns t hzoe oe high to high-z [8, 9] 5ns t lzce ce low to low-z [9] 3ns t hzce ce high to high-z [8, 9] 5ns t pu ce low to power up 0 ns t pd ce high to power down 10 ns t dbe byte enable to data valid 5 ns t lzbe byte enable to low-z 0 ns t hzbe byte disable to high-z 6 ns notes 5. ac characteristics (except high-z) are te sted using the load conditions shown in fi gure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 7. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 8. t hzoe , t hzce , t hzbe and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads.transition is measured when the outputs enter a high impedance state. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe , and t hzwe is less than t lzwe for any given device. 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 50 1.5v (a) 3.3v output 5 pf ( c) r 317 r2 351 high-z characteristics (b) [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 5 of 11 data retention waveform write cycle [10, 11] t wc write cycle time 10 ns t sce ce low to write end 7 ns t aw address setup to write end 7 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 7 ns t sd data setup to write end 5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [9] 3ns t hzwe we low to high-z [8, 9] 5ns t bw byte enable to end of write 7 ns data retention characteristics over the operating range parameter description conditions [12] min max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 20 ma t cdr [4] chip deselect to data retention time 0 ns t r [13] operation recovery time t rc ns ac switching characteristics [6] over the operating range (continued) parameter description ?10 unit min max 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc notes 10. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 12. no inputs may exceed v cc + 0.3v 13. full device operation requires linear v cc ramp from v dr to v cc (min) > 50 s or stable at v cc (min) > 50 s. [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 6 of 11 switching waveforms read cycle no. 1 [14, 15] read cycle no. 2 (oe controlled) [15, 16] notes 14. device is continuously selected. oe , ce , bhe or bhe or both= v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 7 of 11 write cycle no. 1 (ce controlled) [17, 18] write cycle no. 2 (ble or bhe controlled) notes 17. data i/o is high-impedance if oe or bhe or ble or both = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 8 of 11 write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high-z read lower bits only active (i cc ) l l h h l high-z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high-z write lower bits only active (i cc ) l x l h l high-z data in write upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1051dv33-10baxi 51-85106 48-ball fbga (pb-free) industrial CY7C1051DV33-10ZSXI 51-85087 44-pin tsop ii (pb-free) please contact your local cypress sales repr esentative for availability of these parts. [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 9 of 11 package diagrams figure 1. 48-ball fbga (7.00 mm x 8.5 mm x 1.2 mm) (51-85106) a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max. c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 7.000.10 8.500.10 a 8.500.10 7.000.10 b 1.875 2.625 0.36 51-85106-*e [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. figure 2. 44-pin tsop ii (51-85087) package diagrams (continued) 51-85087-*a [+] feedback [+] feedback
preliminary cy7c1051dv33 document #: 001-00063 rev. *c page 11 of 11 document history page document title: cy7c1051dv33 8-mbit (512k x 16) static ram document number: 001-00063 rev. ecn no. issue date orig. of change description of change ** 342195 see ecn pci new data sheet *a 380574 see ecn syt redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 110, 90 and 80 ma to 110, 100 and 95 ma for 8, 10 and 12 ns speed bins respectively i cc (ind?l): changed from 110, 90 and 80 ma to 120, 110 and 105 ma for 8, 10 and 12 ns speed bins respectively changed the capacitance values from 8 pf to 10 pf on page # 3 *b 485796 see ecn nxr changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed -8 and -12 speed bins from product offering, removed commercial operating range option, modified maximum ratings for dc inpu t voltage from -0.5v to -0.3v and v cc + 0.5v to v cc + 0.3v changed the description of i ix from input load current to input leakage current. changed t hzbe from 5 ns to 6 ns updated footnote #7 on high-z parameter measurement added footnote #11 updated the ordering information table and replaced package name column with package diagram. *c 866000 see ecn nxr changed ball e3 from v ss to nc in fbga pin configuration [+] feedback [+] feedback

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